ESD/Latch-up

Reliateck can support all your ESD and Latch-up testing requirements. In addition to reliability testing, we can determine where ESD and Latch-up events have occurred using the latest in fault isolation techniques.

An ESD event can destroy an IC in a number of ways, resulting in one or more of these attributes: junction leakage, short, or burn-out; dielectric rupture; resistor-metal interface rupture; resistor/metal fusing; and die surface charging.

Human Body Model (HBM)
The human body model (HBM) is the most commonly used model for characterizing the susceptibility of an electronic device to damage from electrostatic discharge (ESD). The model is a simulation of the discharge which might occur when a human touches an electronic device.

The HBM definition most widely used is the test model defined in the United States military standard, MIL-STD-883, Method 3015.7, and Electrostatic Discharge Sensitivity Classification. This method establishes a simplified equivalent circuit and the necessary test procedures required to model an HBM ESD event.

 
Machine Model (MM)
Machine model discharges occur when charged; conductive surfaces come into contact with ESD sensitive devices. To minimize Machine Model discharges, ensure that all metal surfaces that come into contact with ESD sensitive devices are grounded. Measurements should be made to ensure that moving parts remain grounded throughout the process.

Charged Device Model (CDM)

CDM damage from an electrostatic field occurs when a charged item is brought into close proximity to an ESD sensitive device and the device is then grounded while in the presence of the field. Effective ESD control programs ensure that process required insulators will not induce damaging voltage levels onto the devices being handled.
 

Latch-up/Electrical Overstress (EOS)

Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failure due to latch-up. This test is applicable to NMOS, CMOS, bipolar, all variations and combinations of these technologies. Latch-up is not related to a specific mechanism but is an electrical failure a characteristics occurs when a device is subjected to this test.